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unisonic technologies co., ltd UC3848 linear integrated circuit www.unisonic.com.tw 1 of 11 copyright ? 2011 unisonic technologies co., ltd qw-r103-033.f high performance current mode controllers ? description the utc UC3848 is designed to provide several special enhancements to satisfy the needs, for example, power-saving mode for low standby power ( < 0.3w), frequency hopping , constant output power limiting , slope compensation ,over current protection (ocp), over voltage protection (ovp), over load protection (olp), under voltage lock out (uvlo), short circuit protection (scp) , over temperature protection (otp) etc. ic will be shutdown or can auto-restart in situations. ? features * low startup current (about 22 a) * fixed switching frequency(norm. is 68khz) * frequency hopping for improved emi performance. * lower than 0.3w standby power design * linearly decreasing frequency to 26khz during light load * soft start * internal slope compensation * constant power limiting for universal ac input range * gate output maximum voltage clamp(15v) * max duty cycle 74% * over temperature protection * overload protection * over voltage protection * leading edge blanking * cycle-by-cycle current limiting * under voltage lock out * short circuit protection ? ordering information ordering number lead free halogen free package packing UC3848l-d08-t UC3848g-d08-t dip-8 tube UC3848l-s08-r UC3848g-s08-r sop-8 tape reel
UC3848 linear integrated circuit unisonic technologies co., ltd 2 of 11 www.unisonic.com.tw qw-r103-033.f ? pin configuration out v cc v ref v in cs fb ss 1 2 3 4 8 7 6 5 gnd ? pin description pin no. symbol function 1 ss soft-start 2 fb feedback 3 cs controller current sense input 4 v in connected r vin to line voltage compensating v csth and providing constant output power limiting for universal ac input range 5 gnd ground 6 out output to the gate of external power mos 7 v cc supply voltage 8 v ref inter reference voltage
UC3848 linear integrated circuit unisonic technologies co., ltd 3 of 11 www.unisonic.com.tw qw-r103-033.f ? block diagram ss fb v cc gnd out latch oscillator s rq q driver current limiting pwm comp soft start ovp uvlo reference voltage cs v in 4 7 1 2 5 3 6 leb 8 v ref frequency hopping slope compensation constant power limit olp delay time otp logic control burst mode
UC3848 linear integrated circuit unisonic technologies co., ltd 4 of 11 www.unisonic.com.tw qw-r103-033.f ? absolute maximum ratings (ta 25c, v cc =15v, unless otherwise specified) parameter symbol ratings unit supply voltage v cc 30 v input voltage to v in pin v in 30 v input voltage to fb pin v fb -0.3 ~ 6.2 v input voltage to cs pin v cs -0.3 ~ 2.8 v junction temperature t j +150 c operating temperature t opr -40 ~ +125 c storage temperature t stg -50 ~ +150 c note: absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? recommended operating conditions parameter symbol ratings unit supply voltage v cc 8.2 ~ 22 v ? electrical characteristics (ta 25c, v cc =15v, unless otherwise specified) parameter symbol test conditions min typ max unit supply section start up current i str v cc =v thd(on) -0.1v 22 45 a off i off v ss = 0, i fb = 0 7 9 ma supply current with switch on i on v ss = 5v, i fb = 0 7 9 ma under-voltage lockout section start threshold voltage v thd(on) 13.5 14.2 15 v min. operating voltage v cc(min) 7.5 8.2 9 v hysteresis v cc(hy) 6 v internal voltage reference reference voltage v ref measured at pin v ref 6.3 6.5 6.7 v control section v min 0.5 v v fb operating level v max 4.4 v burst-mode enter fb voltage v fb-in v cs =0 1.5 v reduce-frequency end fb voltage v fb-end v cs =0 1.6 v burst-mode out fb voltage v fb-out v cs =0 1.7 v normal v fb = 4v 61 68 75 khz switch frequency power-saving f (sw) before enter burst mode 20 40 khz d max v fb =4.4v,v cs =0 68 74 80 % duty cycle d min v fb < 0.5v 0 % feedback resistor r fb v fb =0v 16 21 26 k soft-start time t ss c ss =0.47uf 9.9 11.2 12.6 ms protection section v ovp1 v ss < 3.5v, v fb > 5v 19 v ovp threshold v ovp1 v ss =4.8v,v fb =3v 28 olp threshold v fb(olp) v cs > 0v, ss open 4.7 4.9 5.1 v delay time of olp t d-olp c ss =0.47uf 55 62 70 ms otp threshold t (thr) 120 135 150 c ovp disable threshold v ss(deact) v fb > 5v, v cc =22v 3.9 4.1 4.3 v olp enable threshold v ss(act) v fb > 5v 5.1 5.4 5.7 v current limiting section leb t leb 220 ns peak current limitation v cs v fb =4.4v 0.86 1 v threshold voltage for i vin =60ua v sense-l i vin =60ua 0.77 v driver output section output voltage low state v ol i source = 200 ma 2.5 v output voltage high state v oh i sink = 200 ma 12.2 v output voltage rise time t r c l = 1.0 nf 200 300 ns output voltage fall time t f c l = 1.0 nf 50 90 ns
UC3848 linear integrated circuit unisonic technologies co., ltd 5 of 11 www.unisonic.com.tw qw-r103-033.f ? functional description the internal reference voltages and bias circuit work at v cc > v thd (on) , and shutdown at v cc < v cc (min) . (1) soft-start when every ic power on, driver output duty cycle will be decided by voltage v ss on soft-start capacitor and v cs on current sense resistor at beginning. after v ss reach 4.2v, the whole soft-star t phase end, and driver duty cycle depend on v fb and v cs . the relation among v ss , v fb and v out as followed fig.3. furthermore, soft-start phase should end before v cc reach v cc (min) during v cc power on. otherwise, if soft-start phase remain not end before v cc reach v cc (min) during v cc power on, ic will enter aut o-restart phase and not set up v out . so the value of c ss should be between 0.1 fand 4.7 f. finally soft-start also set ovp1 active phase. ovp1 active phase between 0 and v ss(deact) , ovp1 will not be sensed after v ss reach v ss(deact) .the soft-start phase t ss t ss = 23.8c ss (ms) (example: c ss =0.47 f, then t ss =23.80.47=11.2ms). fig.3 soft-start phase
UC3848 linear integrated circuit unisonic technologies co., ltd 6 of 11 www.unisonic.com.tw qw-r103-033.f ? functional description(cont.) (2) switch frequency set the maximum switch frequency is set to 68khz. switch frequency is modulated by output power p out during ic operating. at no load or light load cond ition, most of the power dissipation in a switching mode power supply is from switching loss on the mosfet transisto r, the core loss of the transformer and the loss on the subber circuit. the magnitude of power loss is in proportion to the number of sw itching events within a fixed period of time. so lower switch frequency at lower load, which more and more improve ic?s efficiency at light load. at from no load to light load condition, the ic will operate at from burst m ode to reducing frequency mode. the relation curve between f sw and p out /p out (max) as followed fig.4. fig.4 the relation curve between f sw and relative output power p out / p out (max) (3) internal synchronized slope compensation built-in slope compensation circuit adds voltage ra mp onto the current sens e input voltage for pwm generation, this greatly improves t he close loop stability at ccm and prevents the sub-harmonic oscillation and thus reduces the output ripple voltage.
UC3848 linear integrated circuit unisonic technologies co., ltd 7 of 11 www.unisonic.com.tw qw-r103-033.f ? functional description(cont.) (4) frequency hopping for emi improvement the frequency hopping is implemented in the ic; there are two oscillators built-in the ic. the first oscillator is to set the normal switching frequency; the switching frequ ency is modulated with a period signal generated by the 2nd oscillator. the relation betwe en the first oscillator and t he 2nd oscillator as followed fig.5. so the tone energy is evenly spread out, the spread spectrum minimizes the conduction band emi and therefor e eases the system design in meeting stringent emi requirement. fig.5 frequency hopping (5) constant output power limit when the sense voltage, acro ss the sense resistor r s , reaches the threshold volt age, around 0.8v, the output gate drive will be turned off after a small propagation delay t d . this propagation delay will introduce an additional current proportional to t d v in /lp. since the propagation dela y is nearly constant regardl ess of the input line voltage v in . higher input line voltage will result in a larger additional current and hence the output power limit is also higher than that under low input line vo ltage. to compensate this variation for wi de ac input range, the threshold voltage is adjusted by the v in current. since v in pin is connected to the rectified i nput line voltage through a resistor r vin , a higher line voltage will generate higher v in current into the v in pin. the threshold volt age is decreased if the v in current is increased. smaller threshold voltage, forces the output gate drive to termi nate earlier, thus reduce the total pwm turn-on time and make the output power equal to that of low line input. this proprietary internal compensation ensures a constant output power limit for wide ac input voltage from 90vac to 264vac. (6) driver output section the driver-stage drives the gate of the mosfet and is optimized to minimize emi and to provide high circuit efficiency. this is done by reducing the switch on slope when reaching the mosfet threshold. this is achieved by a slope control of the rising edg e at the driver?s output. the output driver is clamped by an internal 15v zener diode in order to protect power mosfet transisto rs against undesirable gate over voltage. (7) protection section the ic takes on more protection functions such as olp, ovp and otp etc. in case of those failure modes for continual blanking time, the driv er is shut down. at the same time, ic enters auto-restart, v cc power on and driver is reset after v cc power on again. otp otp will shut down driver when junction temperature t j > t (thr) for continual a blanking time.
UC3848 linear integrated circuit unisonic technologies co., ltd 8 of 11 www.unisonic.com.tw qw-r103-033.f ? functional description(cont.) (7)protection section (cont.) olp after soft-start phase end, ic will shutdown driver if over load state occurs for continual t d-olp . olp function will not inactive during soft-start phase. olp case as followed fig. 6. the test circuit as followed fig.8. t d-olp =5.53t ss. ovp there are two kinds of ovp circuits, the first ovp function are enabled only when v ss < v ss (deact) & v fb > v fb(olp) during soft-start phase. during above condition, driv er will be shutdown if over voltage state occurs (v cc > v ovp1 ) for continual a blanking time. the first ovp function will not inactive after soft-start phase. the second ovp will shutdown the switching of the power mosfet whenever v cc > v ovp2 . the first ovp case as followed fig.7. the test circuit as followed fig. 9. fig.6 olp case fig.7 ovp case fig.8 olp test circuit fig.9 ovp test circuit
UC3848 linear integrated circuit unisonic technologies co., ltd 9 of 11 www.unisonic.com.tw qw-r103-033.f ? typical application circuit f1 line neut 8 9 10 1 2 3 4 l2 12v/1.25a gnd 5 3 2 6 ic1 6 7 4 3 1 2 l1 1 2 34 t1 ic3 ic2 bd1 t znr1 1 2 3 4 15w tr1 v in ss gnd out fb cs 4 1 7 v cc xc1 r1 r2 c1 r5 r3 r4 d1 c2 yc1 r6 c8 c4 d2 c5 r11 ld1 c10 r12 c6 c7 r13 d3 c3 r7 c9 r14 r8 r9 r10 1 2 3 4 l3 m1 fig.12 UC3848 typical application circuit table1 components reference descrip tion for UC3848 application circuit designator part type designator part type designator part type c1 33 f r1 2.2m ? d1 fr107 c2 0.001 f r2 2.2m ? d2 sb5100 c3 22 f r3 68k ? d3 rs1d c4 470 f r4 100 ? ic1 UC3848 c5 470 f r5 1m ? ic2 pc-817 c6 0.1 f r6 15 ? ic3 tl431 c7 0.01 f r7 560 ? yc1 222 c8 0.001 f r8 1k ? t1 ee25 c9 0.1 f r9 3.9k ? l1 uu10.5 c10 220 f r10 15k ? l2 2 h r11 10k ? l3 ring choke r12 1.5m ? ~4m ? ld1 led r13 1.0 ? f1 2a/250v r14 1.8k ? znr1 7d471k tr1 sck102r55a xc1 334/275v bd1 kbp205
UC3848 linear integrated circuit unisonic technologies co., ltd 10 of 11 www.unisonic.com.tw qw-r103-033.f ? typical characteristics feedback voltage during loadjump from 10% up to 100% load (v ac =90v) feedback voltage during loadjump from 10% up to 100% load (v ac =264v) startup with full load condition at v ac =90v, v ss and v out startup with full load condition at v ac =264v, v ss and v out startup behavior at nominal load condition v ac =90v startup behavior at nominal load condition v ac =264v 0 2000 0 -2v 2v time (400 s/div) 4v 6v 8v 10v 12v 0 -2v 2v 4v 6v 8v 10v 12v time (10ms/div) 0 50 100 0 5v 10v 0 2v 4v time (10ms/div) 0 50 100 0 5v 10v time (4ms/div) 020 40 0 2v 4v 0 2v 4v time (4ms/div) 020 40 0 2v 4v 0 2v 4v 4000 0 2000 time (400 s/div) 4000 6v 8v 6v 8v 6v 8v v ss v out v ss v out 0 2v 4v 6v 8v v ss v fb v ss v fb
UC3848 linear integrated circuit unisonic technologies co., ltd 11 of 11 www.unisonic.com.tw qw-r103-033.f ? typical characteristics(cont.) no load input power vs. line voltage (normal mode) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 100 150 200 250 300 dc input voltage, v in (v) frequency vs. output power 0 20 40 60 80 01234 5 output power, p out (w) 678910 v ac =90v input power no load (po ut =0w) ac input voltage, v in (v) utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.

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